Solutions of the Prior Art and Their Disadvantages
The operating principle of such inductive DC/DC converters is shown by FIGS. 1A and 1B. Such converters conventionally include:                an inductor 10, that in this case has an inductance L=10 μH;        two transistors TN1 and TP1, controlled by a clock signal H;        a load 11;        a filtering capacity C.        
The converter is powered by a continuous supply voltage VCC, and generates at the output a continuous output voltage CVCC. Its operation is regulated by two successive phases, namely:
Phase 1: Energy Accumulation
During this first phase, the transistor TN1 makes it possible to accumulate energy in the inductor 10 by increasing the current passing through it according to the rule dV1=L.dI1/dt1, where dV1 designates the potential difference at the terminals of the inductor 10 during this first phase. When the control signal H=1, the first transistor TN1 is on and the second transistor TP1 is off. The voltage at the node designated by LI in FIG. 1A is then zero (LI=0), therefore dV1=VCC (where VCC is the supply voltage, also called battery voltage), with dt1 being the time of energy accumulation in the inductor 10.
Phase 2: Energy Discharge
In a second phase of operation, the control signal has the value H=0, the transistor TN1 is off, and the transistor TP1 is on. The inductor 10 then discharges its energy in the load 11, by increasing the voltage at the node L1 so as to prevent a break in the current passing through it. Then dV2=L.dI2/dt2, where dV2 designates the potential difference at the terminals of the inductor 10 during this second discharge phase, dt2 designating the inductor discharge time. This makes it possible to obtain an output voltage CVCC greater than the supply voltage VCC.
FIG. 1B shows, in the upper curve, the change in the current I in the inductor 10, according to the value of the control signal H of transistors TN1 and TP1. The current I thus increases during the phase of energy accumulation in the inductor, during which H=1, and decreases in the energy discharge phase, during which H=0, around a mean current value Imoy.
The sum of the accumulation dt1 and discharge dt2 times form a period T of oscillation of the converter: T=dt1+dt2. During the accumulation, during dt1, dV1=VCC, and during the discharge that lasts dt2, dV2=CVCC−VCC.
In addition, the cyclic ratio of such an oscillation is defined as follows:
  R  =                    dt        ⁢                                  ⁢        1            T        .  
FIGS. 2A and 2B more specifically show the accumulation and discharge phases for an output voltage CVCC=5 V, when the supply voltage is high (VCC=4.5 V), and when the supply voltage is low (VCC=1.5 V). FIG. 3 shows a full diagram of the DC/DC converter of FIG. 1A, presenting the means for generating the clock signal H and for regulating the overall operation of the converter.
In this example, the load 11 of the converter is not shown for the sake of simplification. Two resistors R1 and R2, of which the values are chosen so that
  1  ,            2      ⁢      V        =          5      ⁢      V      *                        R          ⁢                                          ⁢          2                          (                                    R              ⁢                                                          ⁢              2                        +                          R              ⁢                                                          ⁢              1                                )                      ,form a dividing bridge. The clock signal H controlling the on or off state of the transistors TN1 and TP1 is generated by an element 30, called PWM (for “Pulse Width Modulation”) performing the modulation of the cyclic ratio of the converter. This PWM 30 receives, at a first input, a signal CLKDCDC from an oscillator OSC 31, and, at a second input, the signal generated at the output of the differential amplifier 32.
Such a differential amplifier is powered by a reference voltage at 1.2 V, called ref (1.2V), and by the voltage of the node located between the two resistors R1 and R2.
When the output voltage CVCC is greater than 5V (value constituting the objective to be reached at the output), the value of the signal generated at the output of the differential amplifier 32, and provided at the input of the PWM 30, decreases, so that the PWM 30 causes the cyclic ratio of the signal H to the signal CLKDCDC to decrease, by adjusting the time of accumulation dt1 in the inductor 10. Conversely, when CVCC<5 V, the value of the signal generated by the differential amplifier 32 increases so that the PWM causes the cyclic ratio to increase. At equilibrium, the differential amplifier generates a non-zero voltage (called equilibrium voltage) to regulate the PWM 30.
FIGS. 2A and 2B will first be described briefly, before describing in detail the operation of the PWM 30. Each of these figures shows an upper curve representing the change in the current I in the inductor 10, as a function of time, and a lower curve representing the control signal H generated by the PWM 30. As shown by the arrow 20, the PWM 30 can act on the accumulation dt1 and discharge dt2 times in order to adjust the cyclic ratio R according to the operating state of the converter.
FIG. 2A relates to the case in which the supply voltage VCC=4.5 V, and the output voltage CVCC=5 V. In this case, during the accumulation phase, the voltage dV1 at the terminals of the inductor 10 is dV1=VCC=4.5 V, and the charge time dt1 must therefore be very short. The discharge time dt2, by contrast, is long.
FIG. 2B relates to the case in which the supply voltage VCC=1.5 V, and the output voltage CVCC=5 V. In this case, unlike in the previous case, VCC<<CVCC, and the accumulation time dt1 must therefore be longer than the discharge time dt2.
It is noted in this configuration that, if the maximum cyclic ratio
  R  =                    ⅆ        t            ⁢                          ⁢      1                                ⅆ          t                ⁢                                  ⁢        1            +                        ⅆ          t                ⁢                                  ⁢        2            is limited to 50%, the output voltage CVCC cannot be greater than double the supply voltage VCC.
The regulation of the system of FIG. 3 is achieved by the combination of the resistor bridge consisting of R1 and R2, the voltage reference (1.2 V), the differential amplifier 32, the oscillator 31 and the PWM 30. These different elements combined indeed make it possible to adjust the cyclic ratio dt1/T, where it is noted that T is the period of the oscillator T=dt1+dt2.
Such a regulation is achieved when dI1=dI2, which makes it possible to ensure the stability of the mean current Imoy in the inductor 10. Using the following notations, we then have
                    dV        ⁢                                  ⁢                  1          ·          dt                ⁢                                  ⁢        1            L        =                  dV        ⁢                                  ⁢                  2          ·          dt                ⁢                                  ⁢        2            L        ,with VCC*dt1=(CVCC−VCC)*dt2.
It is then deduced that, when the supply voltage VCC decreases, it is necessary, to achieve the regulation, for the accumulation time dt1 to increase and/or for the discharge time dt2 to decrease. Conversely, when the level VCC becomes too high, the accumulation time dt1 decreases (less accumulation) and dt2 increases (more discharge time).
A first disadvantage of this DC/DC converter of the prior art is that it has a natural tendency to be unstable. The loop system shown in FIG. 3 is therefore difficult to produce.
To solve this problem of instability, it has been envisaged to voluntarily cause the regulation levels to oscillate between two levels V1 and V2 (between 4.95 V and 5.05 V, for example). In other words, the output voltage CVCC oscillates between 4.95 V and 5.05 V, instead of being constant and equal to 5 V. The oscillation of the system, while not cancelled out, is thus controlled rather than being left free and/or erratic.
However, a disadvantage of this solution of the prior art is that this slight oscillation in the output voltage CVCC reduces the precision. Moreover, the current consumed on the power supply oscillates and has a tendency to create noise, in particular if the power supply is a battery with a high output resistance. Another disadvantage of this prior art technique is that it is incompatible with a DC/DC converter having a precise overload current control, which current can reach high values so as to move from regulation level V1 to regulation level V2.
To more precisely illustrate these various disadvantages, we will consider the case of a DC/DC converter, as shown in FIG. 3, that generates a continuous output voltage CVCC=5 V, and of which the supply voltage VCC is capable of varying between 5 V and 2.5 V. For example, the power supply is provided by a battery, which generates 5 V when it has just been charged, but of which the voltage falls to 2.5 V when it is discharged, after a certain time of use.
As it is desirable to generate an output voltage of CVCC=5 V, and the DC/DC converter must be capable of functioning with a supply voltage VCC=2.5 V, it is necessary, as shown above, for the cyclic ratio to be at least equal to 50%. Indeed, it is noted that the regulation is achieved when dI1=dI2, i.e. when VCC*dt1=(CVCC−VCC)*dt2, from which it is deduced that
  R  =                              ⅆ          t                ⁢                                  ⁢        1                                          ⅆ            t                    ⁢                                          ⁢          1                +                              ⅆ            t                    ⁢                                          ⁢          2                      =          1      -                        VCC          CVCC                .            
Conversely, when the battery is properly charged, and VCC=4.8 V, we have
      R    =                  1        -                              4.8            ⁢            V                                5            ⁢            V                              =              4        ⁢        %              ,therefore a cyclic ratio of around 5% would be adequate. At this voltage VCC=4.8 V, if the differential amplifier 32 detects an output voltage CVCC that is too low (following a current draw, for example), it will act on the PWM 30 so as to increase the cyclic ratio
  R  =                    ⅆ        t            ⁢                          ⁢      1                                ⅆ          t                ⁢                                  ⁢        1            +                        ⅆ          t                ⁢                                  ⁢        2            of the signal H.
As the reaction time of the complete servo loop of FIG. 3 is long (due to the presence of the inductor 10 in which it is necessary to accumulate energy, before delivering it in order to increase the output voltage CVCC), a plurality of periods may be necessary in order to restore the output voltage CVCC to its level CVCC=5 V. The cyclic ratio R can then reach its maximum (in this case 50%) before the output voltage returns to its level of 5 V.
However, when R=50%, a supply voltage VCC=4.8V generates a very high current in the inductor 10, regulated by the equation dI1=VCC*dt1/L. A very large amount of energy is then accumulated in the inductor 10. When the output voltage CVCC returns to its set point level CVCC=5 V, it is impossible to rapidly reduce the large amount energy accumulated in the inductor 10, even by reducing the cyclic ratio R to a few percent.
There is then a risk of an overshoot, causing a reduction in the maximum cyclic ratio.
Conversely, when the output voltage CVCC becomes too low again, no energy is accumulated in the inductor (or at least an inadequate amount of energy), and an undershoot then takes place.
The succession of overshoots and undershoots are the cause of the instability of the DC/DC converter of the prior art. Moreover, the overload control may be activated even though there is only a low output charge.